Figura professionale: Ingegnere elettronico
|Nome Cognome||: S. I.||Età||: 25|
|Cellulare/Telefono||: Riservato!||: Riservato!|
|CV Allegato||: Riservato!||Categoria CV||: Engineering|
|Sede preferita||: Torino|
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Through Silicon Via (TSV) Description This project concerns: • the mathematical characterization of a TSV • the delay of a single TSV • the crosstalk model (impact on delay) • power estimation • Impact of TSVs on the area of 3D integrated circuits Technology Matlab, LTSpice Digital architectures Description Three projects are developed in Integrated systems architecture course: • FIR filter: ◦ VHDL implementation; synthesis and place&route; hardware optimization techniques • Digital multiplier: ◦ design; VHDL description; Modified Booth Encoding and Dadda tree adder; implementation of this structure with approximated compressors • TTA (Transport-Triggered-Architecture) implementation with TCE (Transport-Triggered-Architecture based Co-design Environment) Technology VHDL, QuartusII, Modelsim, Matlab, Encounter(Innovus), Synopsis AND Gate Description AND gate implementation: • cell design • schematic • layout and characterization Technology Cadence Virtuoso Capacitive microaccelerometer Description The project is structured in: • mathematical characterization of a microaccelerometer • Simulink mechanical/electronic model and electronic reading device model • improvements Technology Matlab, Simulink Butterfly filter Description The project aims to the implementation of a filter performing the FFT: • datapath • microprogrammed control unit Technology VHDL, Modelsim, QuartusII 3D mouse Description The project consists in the implementation of the interfacing between an FPGA and a screen with a VGA input. The aim is to represent on the screen the movement of a microcontroller with a shield equipped with an accelerometer. For the interface part: • I2C protocol (accelerometer-microcontroller) • RS232 protocol (microcontroller-VGA) Technology VHDL, C++, STM32 Nucleo FR401RE, Altera Cyclone II FPGA, Mbed, QuartusII, Modelsim IoT-Ambient Intelligence-Pet care Description The project was developed for the Ambient Intelligence course. The system is a complete automatized system: • controlled by the smartphone • providing food, water and fun to the pet • sending push notifications to the users’ smartphone • http://ami-2016.github.io/PC/ Technology Raspberry, Google Calendar API, Pushetta Digital filter Description Implementation of a digital filer: • datapath • FSM control unit Technology VHDL, QuartusII, Modelsim, FPGA Extra-Curricular Activities and Achievements 2018 Laboratory assistant at Politecnico di Torino 03/2019- present Stage at SPEA SpA Marks Degree mark: 104 Analog and telecommunication electronics: 28 Analog integrated circuits: 28 Integrated systems architecture: 28 Integrated systems technology: 30L Micro & Nano systems: 29 Digital microelectronics : 29 Optoelectronics: 20 Radar and remote sensing: 27 Measurement systems and sensors: 25 Digital integrated systems: 25 Finite element modeling: 28 Radio frequency integrated circuits: 24 Bioinformatics: 25 Thesis work Description My thesis work focuses on the design with High-Level-Synthesis design methodology, of a CIC filter for audio applications. Objective The thesis work is based on the use of the High-Level-Synthesis methodology and focuses on the use of an High-Level-Synthesis tool, Mentor Catapult, to apply the HLS design methodology to an industrial application. In collaboration with the company Silicon Mitus, a CIC filter is developed. The CIC filter is one of the upstream filters in an high-performance DAC for audio application, developed by Silicon Mitus. The thesis goal is to prove that an architecture designed with HLS design methodology, can achieve performance in terms of area, power consumption an timing, which are comparable with the one obtained by an architecture, designed with the classical RTL design flow. The thesis work starts with an introduction to HLS, explaining its concepts, the structures of HLS tools and its advantages over those of RTL design flow. An overview on the structures and the frequency behaviour of the CIC filters is reported, with different CIC filter state-of-the-art architectural solutions. Finally the description of the design flow is introduced and the final results are discussed. The work is finished with the implementation of the CIC filter on the FPGA Xilinx ZedBoard, using Vivado.
Education 2008-2013 Diploma, Liceo Scientifico Ruggero Bonghi, Lucera(FG). 2013-2016 Bachelor degree in Electronic Engineering, Politecnico di Torino, Torino. 2016-2019 Master degree in Electronic Engineering – Microelectronics, Politecnico di Torino, Torino.
Technical Skill Programming Language C, C++, Python basis HDL VHDL, Verilog, SystemVerilog Others Latex, HTML Development Tools Quartus II, Matlab, Codewarrior, Code Blocks, JetBrains PyCharm, Arduino, Vivado, Cadence Virtuoso, Simulink, AWR, Visual Studio Tesiting Tools Cadence Innovus (Encounter), Modelsim, Synopsys, LTSpice Labs Instruments Oscilloscope, Multimeter, Power Supply Concepts Hardware description; RTL design; Digital electronics architectures design; Digital microelectronic design; Microcontrollers programming; FPGA programming, RF, Analog design
Language skill Certification • IELTS 6.0 • Trinity B2.3
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